Complementary Darlington Emitter Follower with Improved Switching Speed and Improved Cross-over Control and Increased Output Voltage

ABSTRACT

In one embodiment, an apparatus includes a first transistor where the base of the first transistor is coupled to an input node. A second transistor is provided where the emitter of the first transistor is coupled to the base of the second transistor and the emitter of the second transistor is coupled to an output node. A third transistor is provided where the base of the third transistor is coupled to the input node. A fourth transistor is provided where the emitter of the third transistor is coupled to the base of the fourth transistor and the emitter of the fourth transistor is coupled to the output node and the base of the second transistor is coupled to the base of the fourth transistor. The base of the second transistor is coupled to the base of the fourth transistor through a shorting link.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. Provisional App. No. 61/424,956 for “Darlington with Intermediate Base Contact” filed Dec. 20, 2010, the contents of which is incorporated herein by reference in their entirety.

BACKGROUND

Particular embodiments generally relate to Darlington transistor configurations.

Use of a complementary darlington pair in an emitter follower configuration has a number of known limitations. Specifically, charge stored in the base of the output transistor restricts switching speed due to the fact that there is no low impedance route by which the charge can be quickly removed. Also, the bases of the two output transistors are not connected by a low impedance link, which means that at the time when one transistors base is changing state from an “OFF” condition to an “ON” condition, the base of the complementary output transistor is not guaranteed to be, and indeed will not be at the same potential, i.e., will not be simultaneously changing from its previously existing “ON” condition to an “OFF” condition. Thus, both transistors are turned on during the cross-over period. This results in a high unwanted “through” conduction current flowing from supply to ground, degrading efficiency. Also, the maximum output voltage swing cannot closely approach that of a single transistor complementary pair because each darlington cannot have less then VBE (˜0.9V) plus VCESAT (˜0.2V) across it's collector emitter when turned on.

SUMMARY

In one embodiment, an apparatus includes a first transistor having a base, an emitter, and a collector, wherein the base of the first transistor is coupled to an input node. A second transistor is provided having a base, an emitter, and a collector, wherein the emitter of the first transistor is coupled to the base of the second transistor and the emitter of the second transistor is coupled to an output node. A third transistor is provided having a base, an emitter, and a collector, wherein the base of the third transistor is coupled to the input node. A fourth transistor is provided having a base, an emitter, and a collector, wherein the emitter of the third transistor is coupled to the base of the fourth transistor and the emitter of the fourth transistor is coupled to the output node and the base of the second transistor is coupled to the base of the fourth transistor. The base of the second transistor is coupled to the base of the fourth transistor through a shorting link.

In one embodiment, A method including: coupling a first transistor to an input node; coupling the first transistor to a base of a second transistor; coupling the second transistor to an output node; coupling a third transistor to the input node; coupling the third transistor to a base of the fourth transistor; and coupling the fourth transistor to an output node, wherein the base of the second transistor is coupled to the base of the fourth transistor through a shorting link.

The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a circuit of a Darlington transistor configuration according to one embodiment.

DETAILED DESCRIPTION

Described herein are techniques for a Darlington transistor configuration. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

FIG. 1 depicts a circuit 100 of a Darlington transistor configuration according to one embodiment. In one embodiment, the Darlington transistor configuration is a complementary Darlington emitter follower pair. Circuit 100 may be used to drive MOSFET and Insulated gate bipolar transistor (IGBT) gates with a high current gain. As shown, circuit 100 includes a first transistor Q11 IN and a second transistor Q11 OUT that may be considered a first Darlington. A complementary Darlington or emitter follower may include transistor Q12 IN and transistor Q12 OUT. In one embodiment, circuit 100 may be a monolithic Darlington configuration. The monolithic configuration means that transistor Q11 IN and Q11 OUT may be included in a single die and transistor Q12 IN and transistor Q12 OUT may be included in a single die. Both dies may be included in a single device. Also, it will be understood that even though a Darlington configuration is described, other similar configurations may be used, such as a triplington or other multiple transistor configurations in a Darlington configuration. Also, NPN and PNP variations of the Darlington transistor configuration may vary.

In circuit 100, an input is coupled to the base of transistor Q11 IN and the base of transistor Q12 IN. Also, an output is coupled to the emitters of transistor Q11 OUT and transistor Q12 OUT. The emitters of transistors Q11 OUT and Q12 OUT may be connected together (shorted) or left unconnected in which case there are two output nodes. Particular embodiments add a link between the base of transistor Q11 OUT and the base of transistor Q12 OUT. The added link may be a wire that provides a short. Adding the link eliminates or reduces a very large wasted shoot-through current at a crossover. At a point in the switching cycle where transistor's Q11 OUT state is being changed from conducting to non-conducting and transistor Q12 OUT is changing from non conducting to conducting, transistor Q11 OUT should turn off at exactly the same time that transistor Q12 OUT turns on. However, due to charge stored in the base of transistor Q11 OUT, transistor Q11 OUT remains turned “ON” for a finite time during which time transistor Q12 OUT and transistor Q11 OUT are both ON simultaneously and present a very low resistance path to ground. During this time, very large shoot through currents flow from supply to ground. These currents are wasted energy and reduce the efficiency of the circuit. The provision of the short from the base of transistor Q11 OUT to the base of Q12 OUT resists the tendency for both transistors to be simultaneously turned on. Also, it provides a very effective route for removal of the stored charge and thus further resists the possibility of transistor Q11 OUT remaining turned on for long enough to permit the flow of the shoot through currents. An identical situation exists when transistor Q12 OUT is turning off and transistor Q11 OUT is turning on.

Also, circuit 100 provides a highest possible switching speed and the highest possible rail to rail excursion. The highest switch speed is due to being able to discharge transistor Q11 OUT or transistor Q12 OUT quickly with the added link. In addition, a turn-off voltage is lowered to about 0.5V and also the turn-on voltage is within 0.5V of supply Vcc. Conventionally, the turn off voltage or turn on voltage would not be lower than one VBE+one VCESAT ˜0.9V, where VBE is the base-emitter voltage and VCESAT is the collector-emitter voltage at saturation. This is because the base of the output transistor Q11 OUT or transistor Q12 OUT is required to be at approximately 0.7V above its emitter voltage for base current to flow to create current flow in its emitter-collector circuit. Additionally this base current is supplied by the input transistor Q12 IN via its emitter-collector circuit. In a monolithic, or discrete darlington configuration, the collector of the input transistor Q12 IN is connected to the collector of the output transistor Q12 OUT. Hence the voltage difference between the emitter of transistor Q12 IN (which is also the base of transistor Q12 OUT) and its collector cannot be less than the VCESAT of transistor Q12 IN, say 0.2V, otherwise transistor Q12 IN will not conduct the needed base current into the base of transistor Q12 OUT. Given that the emitter of transistor Q12 OUT has to be approximately 0.7V below its base and its base has to be 0.2V below its collector then the collector emitter voltage of transistor Q12 OUT when conducting cannot be less than approximately 0.7V plus 0.2V, that is—VBESAT(of transistor Q12 OUT) plus VCESAT(of transistor Q12 IN).

A wire may be used to couple the base of transistor Q11 OUT and the base of transistor Q12 OUT together. The wire permits the characteristics of the Darlingtons to be modified as desired. Additional components other than the wire may be added with the wire or used in lieu of the wire.

Also, an additional pad may be provided such that the wire may be added to link transistor Q11 OUT and transistor Q12 OUT when a monolithic darlington design is used. The additional pad may not be necessary if a monolithic darlington design is used. The Darlingtons may be cascaded where additional pads may or may not be provided such that each intermediate base may or may not be connected to an additional component.

Without using the added link, it is possible that transistors Q11 OUT and Q12 OUT were on at the same time. This is because the bases of transistor Q11 OUT and transistor Q12 OUT do not have a low resistance route by which charge stored in their bases can be removed rapidly. Whichever transistor is turned “ON” contains significant stored charge that must be removed before its voltages will start to change. If the base bias difference reaches around 1.2V, both transistors Q11 OUT and Q12 OUT are on. This causes a current to flow from power supply Vcc to ground through transistors Q11 OUT and Q12 OUT. This is a high parasitic current, which wastes power.

The link causes the bases of transistors Q11 OUT and Q12 OUT to be at the same voltage and provides a route for the rapid removal of the stored base charge. Thus, transistor Q11 OUT and transistor Q12 OUT do not turn on at the same time. Thus, a very large parasitic current does not flow from power supply Vcc to ground.

The added link also allows the switching performance of the Darlington transistor to be fast. The switching performance may be dependent upon charge stored in the base region of transistor Q11 OUT. If the base region of transistor Q11 OUT is floating, then the time in which the charge can dissipate may limit switching times to turn off transistor Q11 OUT from an on state. However, the added link allows charge to be dissipated faster from the base region to turn off transistor Q11 OUT. For example, transistor Q12 IN turns on, and couples the base of transistor Q11 OUT to ground. This dissipates the charge at the base of transistor Q11 OUT to decrease the switching time to turn off transistor Q11 OUT. The discharge is performed for transistor Q12 OUT through transistor Q11 IN but in the opposite direction.

As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims. 

1. An apparatus comprising: a first transistor having a base, an emitter, and a collector, wherein the first transistor coupled to an input node; a second transistor having a base, an emitter, and a collector, wherein the first transistor is coupled to the base of the second transistor and the second transistor is coupled to an output node; a third transistor having a base, an emitter, and a collector, wherein the third transistor is coupled to the input node; and a fourth transistor having a base, an emitter, and a collector, wherein the third transistor is coupled to the base of the fourth transistor and the fourth transistor is coupled to the output node, wherein the base of the second transistor is coupled to the base of the fourth transistor through a shorting link.
 2. The apparatus of claim 1, wherein: the base of the first transistor coupled to the input node; the emitter of the first transistor is coupled to the base of the second transistor and the emitter of the second transistor is coupled to the output node; the base of the third transistor is coupled to the input node; and the emitter of the third transistor is coupled to the base of the fourth transistor and the emitter of the fourth transistor is coupled to the output.
 3. The apparatus of claim 1, wherein the shorting link removes charge stored in the base of second transistor or the fourth transistor.
 4. The apparatus of claim 1, wherein removing the charge causes the second transistor to turn “OFF” when the fourth transistor is turning on.
 5. The apparatus of claim 1, wherein the shorting link discharges the second transistor or the fourth transistor when either the second transistor or the fourth transistor is turning off.
 6. The apparatus of claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor is a complementary Darlington emitter follower pair.
 7. The apparatus of claim 1, the first transistor, the second transistor, the third transistor, and the fourth transistor are formed in a monolithic Darlington configuration.
 8. The apparatus of claim 7, wherein the first transistor and second transistor are included in a first die and third transistor and the fourth transistor are included in a second die.
 9. The apparatus of claim 1, wherein the first die and the second die are included in a single device.
 10. The apparatus of claim 1, wherein the shorting link comprises a wire.
 11. The apparatus of claim 1, wherein the shorting link comprises a wire that is coupled to an additional component.
 12. The apparatus of claim 1, wherein the bases of second and the fourth transistors are at the same voltage due to the shorting wire.
 13. A method comprising: coupling a first transistor to an input node; coupling the first transistor to a base of a second transistor; coupling the second transistor to an output node; coupling a third transistor to the input node; coupling the third transistor to a base of the fourth transistor; and coupling the fourth transistor to an output node, wherein the base of the second transistor is coupled to the base of the fourth transistor through a shorting link.
 14. The method of claim 13, further comprising: coupling the base of the first transistor the input node; coupling the emitter of the first transistor to the base of the second transistor and the emitter of the second transistor to the output node; coupling the base of the third transistor to the input node; and coupling the emitter of the third transistor to the base of the fourth transistor and the emitter of the fourth transistor to the output.
 15. The method of claim 13, wherein further comprising removing the charge causing the second transistor to turn “OFF” when the fourth transistor is turning on.
 16. The method of claim 13, wherein the shorting link discharges the second transistor or the fourth transistor when either the second transistor or the fourth transistor is turning off.
 17. The method of claim 13, wherein the shorting link comprises a wire.
 18. The method of claim 13, wherein the shorting link comprises a wire that is coupled to an additional component.
 19. The method of claim 13, wherein the bases of second and the fourth transistors are at the same voltage due to the shorting wire. 